(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making an improved ultra-thin silicon nitride-oxide gate insulating layer for field effect transistors with deep submicrometer channel lengths.
(2) Description of the Prior Art
Advances in the semiconductor process technologies in the past few years have dramatically decreased the device feature sizes and increased circuit density on integrated circuit chips. The device used the most for these Ultra Large Scale Integration (ULSI) applications is the Field Effect Transistor (FET) which consists of a polysilicon or polycide gate electrode formed over a thin gate oxide with self-aligned source/drain contact areas. The popular choice of FETs is because of their very small size, high packing density, low power consumption, high yields, and low cost of manufacturing.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single-crystal semiconductor substrate. As the size of the polysilicon gate electrode structure is scaled down in the horizontal direction to provide submicrometer FET channel lengths to increase circuit density and speed, it is also necessary to scale back in the vertical dimensions. Therefore it is necessary to form more shallow source/drain junctions and it is also necessary to reduce the gate oxide thickness (T.sub.ox) for reduced gate voltage (V.sub.g).
However, as the FETs are down scaled to submicrometer channel length, the FET device experiences a number of undesirable electrical characteristics results. Besides the need to minimize the various short channel effects, it is also necessary to minimize the oxide leakage current through the FET ultra-thin gate oxide. As the gate oxide thickness is scaled down approaching thicknesses less than 16 Angstroms, direct electron tunneling through the gate oxide occurs. When this oxide leakage current becomes comparable to the FET off-current (I.sub.off), the standby power for the FET becomes unacceptably high.
Numerous methods for making improved ultra-thin gate oxides have been reported in the literature. For example, in U.S. Pat. No. 5,324,675 to Hayabuchi, a method is described for making a MONOS (metal-oxide/nitride/oxide-silicon) gate insulating layer for non-volatile memory. The method grows a thin oxide and deposits a silicon nitride. The silicon nitride is then partially oxidized to form an oxide/nitride/oxide gate oxide for non-volatile memory. A polysilicon gate electrode and the thin silicon nitride layer adjacent to the gate electrode are oxidized to from a silicon oxide which can be removed without damaging the source/drain areas. The oxide/nitride/oxide gate insulating layer remains under the gate electrode to form a non-volatile memory cell. Another method of making thin gate oxides is described in U.S. Pat. No. 5,650,344 to Ito et al. and in U.S. Pat. No. 5,808,348 to Ito et al. Ito teaches a method for a non-uniform nitrided gate oxide structure in which the gate insulating layer remains essentially pure silicon oxide under the center of the gate electrode while the gate insulator is nitrogen-rich at the edge of the gate electrodes.
In recent years there has been an increasing interest in making ultra-thin gate oxides using a new low-pressure (reduced pressure) rapid thermal process (LP-RTP) technique, commonly referred to as in-situ steam generation (ISSG). In this method an in-situ steam is generated from ultra-pure hydrogen (H.sub.2) and oxygen (O.sub.2) at low pressures to controlably grow gate oxides that are less than 25 Angstroms thick.
However, there is still a strong need in the semiconductor industry to form ultra-thin gate oxides for FETs with improved low leakage currents and with increased processing latitude (windows) using LP-RTP while maintaining a cost-effective manufacturing process.